This invention relates generally to the field of computer graphics, and more particularly, to optimizing texture tag checking for three-dimensional computer graphics.
Many applications of modern computer graphics strive to create three-dimensional images on a display device (e.g., a computer monitor) in order to provide a realistic virtual environment. In a typical imaging technique, a three-dimensional object is created by connecting a number of two-dimensional polygons, such as, for example, triangles. Each polygon defines a surface which can be assigned or given a texture, such as wood, stone, fur, hair, scales, and the like, to enhance the realism of the generated object. Data or information for each texture can be stored in a cache memory and retrieved as necessary to produce the texture on applicable polygons. Different techniques have been developed for accessing the texture information from cache memory. These previously developed techniques, however, are problematic in that they require a relatively large number of logic operations to be performed. Furthermore, if a three-dimensional graphics system is implemented at least in part as an integrated circuit (IC) device, this requirement for a large number of logic operations necessitates large amounts of surface area and more time for processing of such IC device.
According to one embodiment of the present invention, a circuit for tag checking includes a first comparison gate which compares a first dimension field of a tag with a first dimension element for a group of texels associated with a sample point. A second comparison gate compares a second dimension field of the tag with a second dimension element for the group of texels. A logic gate, coupled to each of the first and second comparison gates, is associated with one texel of the group of texels. The logic gate outputs a predetermined signal if the first and second dimension fields of the tag are the same as the first and second dimension elements, respectively.
A technical advantage of the present invention includes reducing the number of logic operations (and corresponding logic gates) required in order to perform a tag checking process. This can be accomplished, at least in part, by comparing a first dimension (e.g., u) field of a tag with a first dimension (or u) element for a group of texels associated with a sample point and, in a separate operation, comparing a second dimension (or v) field of the tag with a second dimension (or V) element for the same group of texels. Other important technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.